From 637c2646e27848222b9f2c94d663449678b1d7f1 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 26 Jun 2015 15:05:50 +0200 Subject: [PATCH] x86/AMD: also print TOM2 when printing MTRR state ... to have a complete picture of cachability settings. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- xen/arch/x86/cpu/mtrr/generic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c index 493830b58c..935f0a0e8a 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -182,6 +182,18 @@ static void __init print_mtrr_state(const char *level) else printk("%s %u disabled\n", level, i); } + + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD + && boot_cpu_data.x86 >= 0xf) { + uint64_t syscfg, tom2; + + rdmsrl(MSR_K8_SYSCFG, syscfg); + if (syscfg & (1 << 21)) { + rdmsrl(MSR_K8_TOP_MEM2, tom2); + printk("%sTOM2: %012"PRIx64"%s\n", level, tom2, + syscfg & (1 << 22) ? " (WB)" : ""); + } + } } /* Some BIOS's are fucked and don't set all MTRRs the same! */ -- 2.30.2